(1) Field of the Invention
This invention relates generally to a flexible voltage transient detector circuit with two different critical points, and more particularly to a voltage transient detector circuit with a simple pattern and a delay time which can be set flexibly as needed.
(2) Description of the Prior Art
Because of the continuous shirkage in today's device manufacture technology, a lot of electronic circuits can be put together in an tiny integrated circuit (IC) chip. A sudden change in the environment of the system such as voltage transients in the primary supply voltage, may result in an abnormal operation of the integrated circuit, and thus affect the reliability of the products.
Accordingly, a voltage transient detector circuit can be provided for solving the above mentioned problem. When the system itself is disturbed by the aforementioned undesired voltage transients, the detector circuit can immediately detect the change and further prevent the error operation of the integrated circuit. Once the supply voltage returns its regular condition, the integrated circuit can be continuously manipulated in the normal mode.
One of the traditional types of the voltage transient detector circuit is shown in FIG. 1A. The detector circuit comprises an initialization unit 11, producing an output INIT for deciding the integrated circuit 10 to operate in the normal mode or the initialized mode; and a comparator 13, connected to the input of the above initialization unit 11 for resetting the initialization unit 11 and thus making the integrated circuit 10 to return the initialized mode. The comparator 13 with a noninverting input connected to a reference voltage V.sub.ref, and an inverting input connected to a power supply 17 can compare the power voltage V.sub.DD with the reference voltage V.sub.ref.
A level shifter 15 can be optionally added in between the power supply 17 and the comparator 13 for lowering the power voltage V.sub.DD to a constant voltage V.sub.DD -L.S (L.S is referred as the voltage across said level shifter). The lowered voltage is then convenient for comparing with the reference voltage V.sub.ref. When the output of the initialization unit 11 is non-active, the INIT value is 0, and the integrated circuit 10 stays in the normal mode. On the other hand, when the output of the initialization unit 11 is active, the INIT value is 1, and the integrated circuit 10 goes back to the initialized mode.
Referring to FIG. 1B, there is shown a timing chart corresponding to the circuit of FIG. 1A. In the beginning when the power supply 17 is steady and the power voltage V.sub.DD stays at a normal value (denoted as A1 in FIG. 1B), the output of the initialization unit 11 is non-active, INIT=0, and the integrated circuit 10 is in the normal condition. Once the power voltage V.sub.DD suddenly drops below its critical point (it means V.sub.DD -L.S.+-.V.sub.ref) which is denoted as B1 in FIG. 1B, the comparator 13 will produce an output signal to reset the initialization unit 11 and make it to produce an active output wherein INIT=1. At the same time the integrated circuit 10 is in the initialized mode that means the device returning to the initial state and to wait for further orders. When the power voltage V.sub.DD rises above the critical point which is denoted as C1 in FIG. 1B, the comparator 13 will also generate an output signal to the initialization unit 11 and make it into the non-active state wherein INIT=0, and the integrated circuit 10 will go back to the regular condition.
However, if the power voltage V.sub.DD becomes unsteady and constantly goes up and down near the critical point (denoted as the vibrating curve between points C1 and D1 in FIG. 1B), the states of the integrated circuit 10 would be changed between the initialized mode and the normal mode all the time that result in the unpredictable status of the integrated circuit 10. Also, when the power voltage rises from the voltage below the critical point (B1) to that above the critical point (C1), the integrated circuit 10 will immediately back from the initialized mode to the normal mode. This will further cause the melt functions of the integrated circuit 10 due to inadequate time to return the normal condition.